In conventional computer systems, the central processing unit (CPU) is usually much faster than the main memory. In order to avoid having the CPU stop and wait for the slower main memory each time it tries to write a word into the main memory, a conventional queue circuit is often provided to accept and temporarily store a word from the CPU as fast as the CPU can output the word so that the CPU does not have to stop and wait, and then the queue circuit subsequently stores the word in main memory while the CPU is carrying out other processing.
In conventional systems, the maximum number of data words which the queue circuit can accept and store is normally a fixed number. For example, there are queue circuits which can temporarily store only one data word, as a result of which the queue circuit must transfer the stored data word to the main memory before the queue circuit can accept a further data word from the CPU.
It is an object of the present invention to provide a queue circuit in which the maximum number of words the queue circuit is permitted to store when turned on can be selectively varied.
It is a further object of the invention to provide such a queue circuit which can be selectively turned off.
It is a further object of the invention to provide such a queue circuit which involves minimal additional hardware or software in comparison to conventional queue circuits, and which is thus relatively inexpensive to incorporate into a computer system.
The objects and purposes of the invention, including those set forth above, are met by providing a method and apparatus in which a predetermined maximum number of words can be accepted from a first arrangement and temporarily stored and then subsequently transferred to a second arrangement, wherein the maximum number of words can be selectively set to at least two different values which are integers greater than or equal to zero.